OPENSSL_ia32cap - the x86[_64] processor capabilities vector env OPENSSL_ia32cap=... <application> OpenSSL supports a range of x86[_64] instruction set extensions and features. These extensions are denoted by individual bits or groups of bits stored internally as ten 32-bit capability vectors and for simplicity represented logically below as five 64-bit vectors. This logical vector (LV) representation is used to streamline the definition of the OPENSSL_ia32cap environment variable. Upon toolkit initialization, the capability vectors are populated through successive executions of the CPUID instruction, after which any OPENSSL_ia32cap environment variable capability bit modifications are applied. After toolkit initialization is complete, populated vectors are then used to choose between different code paths to provide optimal performance across a wide range of x86[_64] based processors. Further CPUID information can be found in the Intel(R) Architecture Instruction Set Extensions Programming Reference, and the AMD64 Architecture Programmer's Manual (Volume 3).

Notable Capability Bits for LV0
The following are notable capability bits from logical vector 0 (LV0) resulting from the following execution of CPUID.(EAX=01H).EDX and CPUID.(EAX=01H).ECX:

Notable Capability Bits for LV1
The following are notable capability bits from logical vector 1 (LV1) resulting from the following execution of CPUID.(EAX=07H,ECX=0H).EBX and CPUID.(EAX=07H,ECX=0H).ECX:

Notable Capability Bits for LV2
The following are notable capability bits from logical vector 2 (LV2) resulting from the following execution of CPUID.(EAX=07H,ECX=0H).EDX and CPUID.(EAX=07H,ECX=1H).EAX:

Notable Capability Bits for LV3
The following are notable capability bits from logical vector 3 (LV3) resulting from the following execution of CPUID.(EAX=07H,ECX=1H).EDX and CPUID.(EAX=07H,ECX=1H).EBX:

Notable Capability Bits for LV4
The following are notable capability bits from logical vector 4 (LV4) resulting from the following execution of CPUID.(EAX=07H,ECX=1H).ECX and CPUID.(EAX=24H,ECX=0H).EBX:

OPENSSL_ia32cap environment variable
The OPENSSL_ia32cap environment variable provides a mechanism to override the default capability vector values at library initialization time. The variable consists of a series of 64-bit numbers representing each of the logical vectors (LV) described above. Each value is delimited by a ':'. Decimal/Octal/Hexadecimal values representations are supported. "env OPENSSL_ia32cap=LV0:LV1:LV2:LV3:LV4" Used in this form, each non-null logical vector will *overwrite* the entire corresponding capability vector pair with the provided value. To keep compatibility with the behaviour of the original OPENSSL_ia32cap environment variable <env OPENSSL_ia32cap=LV0:LV1>, the next capability vector pairs will be set to zero. To illustrate, the following will zero all capability bits in logical vectors 1 and further (disable all post-AVX extensions): "env OPENSSL_ia32cap=:0" The following will zero all capability bits in logical vectors 2 and further: "env OPENSSL_ia32cap=::0" The following will zero all capability bits only in logical vector 1: "env OPENSSL_ia32cap=:0::::" A more likely usage scenario would be to disable specific instruction set extensions. The '~' character is used to specify a bit mask of the extensions to be disabled for a particular logical vector. To illustrate, the following will disable AVX2 code paths and further extensions: "env OPENSSL_ia32cap=:~0x20000000000" The following will disable AESNI (LV0 bit 57) and VAES (LV1 bit 41) extensions and therefore any code paths using those extensions but leave the rest of the logical vectors unchanged: "env OPENSSL_ia32cap=~0x200000000000000:~0x20000000000:~0x0:~0x0:~0x0" Not all capability bits are copied from CPUID output verbatim. An example of this is the somewhat less intuitive clearing of LV0 bit #28, or ~0x10000000 in the "environment variable" terms. It has been adjusted to reflect whether or not the data cache is actually shared between logical cores. This in turn affects the decision on whether or not expensive countermeasures against cache-timing attacks are applied, most notably in AES assembler module. Not available. Copyright 2004-2021 The OpenSSL Project Authors. All Rights Reserved. Licensed under the Apache License 2.0 (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.