# The cad/qflow port

## qflow-1.4.83 – full end-to-end digital synthesis flow for VLSI ASIC designs

## Description

    A digital synthesis flow is a set of tools and methods used to turn a
    VLSI design written in a high-level behavioral language like Verilog
    or VHDL into a physical circuit, which can either be configuration code
    for an FPGA target or a layout in a specific technology, that would
    become part of an IC.
    Qflow uses a complete and open source tool chain for synthesizing
    digital circuits starting from Verilog source and ending in physical
    layout for a specific target fabrication process.

WWW: http://opencircuitdesign.com/qflow/

Categories:
  cad lang/python lang/tcl

## Library dependencies

## Build dependencies

- cad/graywolf
- cad/magic
- cad/netgen
- cad/opensta
- cad/qrouter
- cad/yosys
- devel/gmake
- lang/python/3.8
- tcl->=8.5,<8.6:lang/tcl/8.5

## Run dependencies

- cad/graywolf
- cad/magic
- cad/netgen
- cad/opensta
- cad/qrouter
- cad/yosys
- lang/python/3.8
- lang/python/3.8,-tkinter
- shells/tcsh
- sysutils/ggrep
- tcl->=8.5,<8.6:lang/tcl/8.5